Long-distance propagation of forces in a cell
What might be the differences, if there is any, between mechanical signaling and chemical signaling in a living cell?
suo group research
A method to analyze dislocation injection from sharp features in strained silicon structures
Stresses inevitably arise in a microelectronic device due to mismatch in coefficients of thermal expansion, mismatch in lattice constants, and growth of materials. Moreover, in the technology of strained silicon devices, stresses have been deliberately introduced to increase carrier mobility. A device usually contains sharp features like edges and corners, which may intensify stresses, inject dislocations into silicon, and fail the device. On the basis of singular stress fields near the sharp features, this letter describes a method to obtain conditions that avert dislocations.
Saturated voids in interconnect lines due to thermal strains and electromigration
Zhen Zhang and Zhigang Suo (Harvard), Jun He (Intel)
Attached is a set of slides presented at ASME Congress, 10 November 2006. Thermal strains and electromigration can cause voids to grow in conductor lines on semiconductor chips. This long-standing failure mode is exacerbated by the recent introduction of low-permittivity dielectrics. We describe a method to calculate the volume of a saturated void (VSV), attained in a steady state when each point in a conductor line is in a state of hydrostatic pressure, and the gradient of the pressure along the conductor line balances the electron wind. We show that the VSV will either increase or decrease when the coefficient of thermal expansion of the dielectric increases, and will increase when the elastic modulus of the dielectric decreases. The VSV will also increase when porous dielectrics and ultrathin liners are used. At operation conditions, both thermal strains and electromigration make significant contributions to the VSV. We discuss these results in the context of interconnect design.
Statistics of Electromigration Lifetime Analyzed Using a Deterministic Transient Model
The electromigration lifetime is measured for a large number of copper lines encapsulated in an organosilicate glass low-permittivity dielectric. Three testing variables are used: the line length, the electric current density, and the temperature. A copper line fails if a void near the upstream via grows to a critical volume that blocks the electric current. The critical volume varies from line to line, depending on line-end designs and chance variations in the microstructure. However, the statistical distribution of the critical volume (DCV) is expected to be independent of the testing variables. By contrast, the distribution of the lifetime (DLT) strongly depends on the testing variables. For a void to grow a substantial volume, the diffusion process averages over many grains along the line. Consequently, the void volume as a function of time, V(t), is insensitive to chance variations in the microstructure. As a simplification, we assume that the function V(t) is deterministic, and calculate this function using a transient model. We use the function V(t) to convert the experimentally measured DLT to the DCV. The same DCV predicts the DLT under untested conditions.
Dynamics of terraces on a silicon surface due to the combined action of strain and electric current
A (001) surface of silicon consists of terraces of two variants, which have an identical atomic structure, except for a 90° rotation. We formulate a model to evolve the terraces under the combined action of electric current and applied strain. The electric current motivates adatoms to diffuse by a wind force, while the applied strain motivates adatoms to diffuse by changing the concentration of adatoms in equilibrium with each step. To promote one variant of terraces over the other, the wind force acts on the anisotropy in diffusivity, and the applied strain acts on the anisotropy in surface stress. Our model reproduces experimental observations of stationary states, in which the relative width of the two variants becomes independent of time. Our model also predicts a new instability, in which a small change in experimental variables (e.g., the applied strain and the electric current) may cause a large change in the relative width of the two variants.
Persistent step-flow growth of strained films on vicinal substrates
We propose a model of persistent step flow, emphasizing dominant kinetic processes and strain effects. Within this model, we construct a morphological phase diagram, delineating a regime of step flow from regimes of step bunching and island formation. In particular, we predict the existence of concurrent step bunching and island formation, a new growth mode that competes with step flow for phase space, and show that the deposition flux and temperature must be chosen within a window in order to achieve persistent step flow. The model rationalizes the diverse growth modes observed in pulsed laser deposition of SrRuO3 on SrTiO3
Compliant thin film patterns of stiff materials as platforms for stretchable electronics
Teng Li, Zhigang Suo, Stephanie P. Lacour, Sigurd Wagner
Journal of Materials Research, 20, 3274-3277 (2005)
Surface effects on thin film wrinkling
A recent discussion here about the effect of surface stress on vibrations of microcantilever has gained some interest from our members. A few years ago, Zhigang and I looked at surface effect on buckling of a thin elastic film on a viscous layer (Huang and Suo, Thin Solid Films 429, 273-281, 2003). Although the physical phenomena (buckling vs vibrations) are different, the conclusion is quite consistent with Wei Hong and Pradeep's comments toward the end of the discussion. That is, surface stress only contributes as a residual stress and thus does not affect the buckling wavelength (frequency in space in analogy to frequency in time for vibrations).
Saturated voids in interconnect lines due to thermal strains and electromigration
Zhen Zhang, Zhigang Suo, Jun He
Thermal strains and electromigration can cause voids to grow in conductor lines on semiconductor chips. This long-standing failure mode is exacerbated by the recent introduction of low-permittivity dielectrics. We describe a method to calculate the volume of a saturated void (VSV), attained in a steady state when each point in a conductor line is in a state of hydrostatic pressure, and the gradient of the pressure along the conductor line balances the electron wind. We show that the VSV will either increase or decrease when the coefficient of thermal expansion of the dielectric increases, and will increase when the elastic modulus of the dielectric decreases. The VSV will also increase when porous dielectrics and ultrathin liners are used. At operation conditions, both thermal strains and electromigration make significant contributions to the VSV. We discuss these results in the context of interconnect design.
This has been published and the related references are listed here:
- Z. Zhang, Z. Suo, and J. He, J. Appl. Physics, 98, 074501 (2005). link
- J. He, Z. Suo, T.N. Marieb, and J.A. Maiz, Appl. Phys. Lett. 85, 4639 (2004). link