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Thermomechanical reliability of microelectronics -- Dissertation and Defense


The microelectronic devices integrate more and more diverse materials in a complicated three-dimensional structure with feature size from nanometers to meters. The performance leaps of these devices are so attractive; meanwhile the reliability issues become more urgent in semiconductor industry. Among all of the reliability issues, the thermal-mechanical aspect is always one major concern. This dissertation will cover the following key issues.

One is the stress concentration that leads to many failure modes. In the microelectronic devices, the integrated diverse materials are of different thermomechanical properties, and usually bonded together to form the sharp features, such as trenches, wedges, corners or junctions. These sharp features can concentrate stresses, which in turn fail the devices in the ways of cracking, debonding, or injecting dislocations, etc. Therefore, the study of the singular stress filed around the sharp features should draw a lot of attention. Usually, the singular stress field is a linear superposition of two modes, one stronger and the other weaker, known as split singularities. A dimensionless parameter, called the local mode mixity, is defined to characterize the proportion of the two modes at the length scale where the processes of fracture occur. We apply the theory of split singularities to the problems such as crack penetration or deflection, dislocation injection into strained silicon, and interfacial delamination due to chip-package interaction. In addition, a remedy to reduce the singularity and to suppress the debonding is verified in flexible electronics —applying coating.

Another long-standing failure mode is voiding in interconnects due to the thermal strains and electromigration. This failure mode is exacerbated by the recent introduction of low-permittivity dielectrics. We describe a method to calculate the volume of a saturated void, attained in a steady state when each point in a conductor line is in a state of hydrostatic pressure, and the pressure gradient balances the electron wind. The results indicate that at operation conditions, both thermal strains and electromigration make significant contributions to the void volume. We discuss these results in the context of interconnect design.

The dissertation and defense slides are attached.



1. Split singularities and cracking path selection. IJSS paper.

2. Dislocation injection in strained silicion. APL paper and JAP paper.

3. Voiding in interconnects due to thermal strains and electromigration. JAP paper.


Roberto Ballarini's picture


a while back I wrote a paper with a student that shows the region dominated by the little-k stress intensity factors associated with cracks impinging interfaces could be quite small when the main crack is in the more compliant half-plane. We showed that "small scale yielding" arguments then break down for such cases at relatively low loads.

 I do not have the .pdf handy. The reference is:

Alberto Romeo and Roberto Ballarini, "A cohesive zone model for cracks terminating at a bimaterial interface," IJSS Vo. 34, No. 11, pp. 1307-1326, 1997.

This paper may be of interest to you and others working on such problems.

Dear Rob,

Thank you very much for your comment. I will study your paper and then reply back.



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