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A method to analyze dislocation injection from sharp features in strained silicon structures

Stresses inevitably arise in a microelectronic device due to mismatch in coefficients of thermal expansion, mismatch in lattice constants, and growth of materials. Moreover, in the technology of strained silicon devices, stresses have been deliberately introduced to increase carrier mobility. A device usually contains sharp features like edges and corners, which may intensify stresses, inject dislocations into silicon, and fail the device. On the basis of singular stress fields near the sharp features, this letter describes a method to obtain conditions that avert dislocations.

SiN on silicon We illustrate the method using an idealized structure. A blanket film of silicon nitride (Si3N4) is grown on the (001) surface of a single-crystal silicon substrate. The film is then patterned into a stripe. Here we use a long stripe, rather than a square pad, so that we can focus on the essentials of the method without the complication of three-dimensional corners of the pad.

When the film covers the entire surface of the substrate, the film is under a uniform stress, and the substrate is stress free. When the film is patterned into a stripe, stress builds up in the substrate, and intensifies at the roots of the edges. It is this intensified stress that injects dislocations into the silicon substrate. We study the singular stress field using eigenfunction expansion developed by Williams, Bogy and others. This linear elastic solution of stress field prevails within an annulus, known as the k-annulus. The overall loading is set by the residual stress and the geometry of the stripe, while the atomic process of emitting dislocations occurs within the process zone. The effect of the overall loading on the atomic process is characterized by a single parameter: the stress intensity factor k. Consequently, dislocations are emitted from the root when the stress intensity factor reaches a critical value, k=kc. The value of kc is a constant specific to the materials and the wedge angle (90 deg in this letter), but is independent of loading (e.g., the residual stress) and overall geometry (e.g., the thickness and the width of the stripe). The critical condition, k=kc, gives a scaling relation between the critical stress and the feature sizes.

We compare out analysis with experiments by Kammler et al and Isomae, and predict the correct trend and order of magnitude. However, we recognize that the good agreement with some of the experimental observations may be fortuitous. Our procedure to estimate kc is crude, and can be improved by using more advanced model such as those due to Rice and others. We also note two effects that can act in opposite directions: thermal activation will decrease the value of kc, while blunt edge roots will increase the value of kc.

We should also remark that, given the uncertainty in the sharpness of the edge root in an actual structure, the value of kc may have a statistical distribution. One may as well forego the unreliable theoretical estimate of kc, and simply use the experiments as a means to determine the value of kc and its statistical distribution. The approach is analogous to that of experimental determination of fracture toughness.

In summary, we have described a method to analyze dislocations emission from sharp features in strained silicon structures. The method predicts the correct orders of magnitude of the critical stress, and gives a scaling relation between the stress level and feature sizes. These predictions call for more systematic comparison between the theory and experiments. Our approach can be applied to other crystallographic orientations, material combinations, and sharp features. The estimate of kc may be improved significantly. The approach may ultimately contribute to the design of strained silicon devices.

Update: This paper has been published on Applied Physics Letter, 89, 261912 (2006). The preprint was attached here on 4 Nov. 2006.


Min Huang's picture

Strained-silicon technology has been successfully used in semiconductor industry to improve the performance of CMOS transistors while their feature size scaling below 100 nm. Stress induced electron/hole mobility change in silicon, known as piezoresistance effect, was first measured 50 years ago. The research on this topic has become very active since late 1980s. Manufacturable strained silicon technology was developed in 1990s. Nowadays, almost every semiconductor manufacturer is using this novel technology to improve the performance of their products.

It is believed that this trend will continue and the stress in CMOS will be pushed to a much higher value since carry mobility is found to follow a superlinear relation with the stress. The stresses in the channel of CMOS come from various sources, such as shallow trench isolation (silica), etch-stop layer (silicon nitride) and epitaxial silicon germanium.

Imagine that hundred millions of transistors are squeezed in a centimeter-size IC chip, and each transistor needs to sustain considerable mechanical stresses and undergo severe process flow. Mechanical failures are conceivable.

This paper targets an important issue: dislocation injection in strained-Si. The dislocations could fail the whole IC chip by electrical leakage if they appear near the channel area. This issue will become critical when higher and higher stresses are induced in the transistors. This is a good opportunity for mechanicians to make significant impacts on this multi-billion dollar industry.

Min, thank you very much for your comments. We realize that there is a lot for us to do in this field. For example:

1. Optimization of design. Higher stress is preferred in the strained silicon to enhance the carrier mobility. However, the high stresses also easily induce the dislocation in silicon, which leads to electrical leakage and hence is so detrimental to the device. There must be an optimum design to compromise the two opposite directions, by changing the geometry, modify the length ratio, or change the materials combinations, etc. Mechanician can definitely give the suggestion for the optimization of design.

2. Nucleation sites of dislocation deserve more attention. Triple junctions are very common in silicon devices, i.e., three different materials meet at a corner. In strained silicon technology, the preferred stresses in silicon are introduced by stressors, e.g. shallow trench isolation (STI), etch stop, silicides, SiGe, etc. The stressors introduce the stresses in silicon, but also concentrate the stresses around those triple junctions. So I guess those triple junctions are dislocation nucleation sites, e.g. the junction of gate-channel-cap. But I am not sure since I did not find any experimental literature to report the nucleation sites in the strained silicon devices. So I think if there are more experimental observations, in situ or not, it will nail down the problem and find the solution. Maybe this is too hard for experimentalists.

3. We are eager to do more, but the problems themselves are not clear to us. So if more people from industry help us to find the problem, then we can contribute more to this multi-billion dollar industry.

Thanks in advance if anybody here can help me.

Min Huang's picture

Two inputs on the problem:

  1. Layout dependence: It is observed that the dislocation caused failures are easy to happen for certain layouts, under which high stresses are induced in strained-Si.
  2. Nucleation sites: The dislocation nucleation sites can be generated in strain-Si by various process steps, such as ion implantation and end-of-range defects caused by implantation annealing. The problem is how to prevent the dislocations to grow and move into channel area during the subsequent high temperature annealing.

Hi, Min,

Thanks a lot about your inputs.

1. Can you be more specific about the layout dependence? For example, give us some literature or some public figures to show the problem with different layouts. Then maybe we can nail down the problem, and make a specific contribution.

2. About the dislocation motion, Zhigang and I discussed some before. But the problems are not clear to us either. We want to do some, but we don't want to cook up some artificial structure to study, but industry does not use it in practice. The knowledge about those processes and problems are bottleneck to me.

Xiao Hu Liu's picture

The paper is interesting and useful to the application in device strain engineering. Here are some comments that the authors may want to elaborate to make it even more useful.

1) Using the stronger term for singular field, can you only fit the interfacial stress well within 10-3 <r/h<10-2 ? If so, using two terms, that is, both stronger and weaker, one may fit the stress well within much larger range, say, up to r/h<10-2 . If I remember it right, this is what I found when I was working on the paper Liu, Suo, and Ma, Acta Mat. (1999). If the stronger term is good only up to r/h=10-2 , the range of validity is only a few A for tens of nanometer h. It is open for debate whether continumm model still works within a few A. The location r=b in the criteria for dislocation injection can be outside the range.

2) The authors may want to look at the effect of periodic pattern of Si3N4 with length L and spacing S. It is of more interest to device strain engineering, since no chip ends up with only an isolated Si3N4 on it, although it is a good ideal model to start with.

Thank you very much. We are doing (1) now, but have not thought about (2). The initial work was inspired by an APL from IBM, and by discussions with several colleagues in the industry.

Our criterion for dislocation is very naive, perhaps not up to the standard of dislocation experts of the day. But agreement with the IBM experiment is encouraging.

Perhaps even more importantly, given the uncertainty of dislocation nucleation, we should really just define kc, and use an experiment to measure it, rather than pretend that we know enough to calculate it. The spirit is the same as the fracture mechanics.

Do you see this as a viable approach?


Xiaohu, thank you very much for your comments and ideas.

1. You mention a very important point about the range of curving fitting, i.e. the range of k-annulus. When I did the fitting, I checked range up to 10-3<r/h<10-1, the fitting was good for all the cases when L/h>2. When we fitted the case of L/h=1, the error is too big due to the perturbation of symmetry boundary condition. Hence, for accuracy and validity, I just used the range of 10-3<r/h<10-2 for all the cases. But in reality, L/h>=2, so the validity range can reach r/h<=10-1. Even the film thickness is just about tens of nanometers, the equation of singular stress field still works.

If you consider the full expansion of power-law eigenfunctions, not only stronger singular term and weaker singular term, but also non-singular term, then no worry about the range of validity of fitting. That is, the location r=b for dislocation injection still works. Meanwhile, there are two or more k’s in evaluating the critical condition of dislocation injection. This makes the criterion not neat and simple to use. But, you are absolutely right. You point out a very important issue, so currently we are trying to use both singular terms to consider more generic cases.

For SiN/silicon system, from evaluation of local mode mixity (i.e. stress ratio of weaker mode to stronger mode, please refer to the paper), the contribution from weaker mode is less than 5% when L/h>2. So the stronger singular term is enough with reasonable error.

2. I thought about effect of periodic spacing in my notebook, sketch some figures qualitatively. We did not include this effect in this paper, because we wanted to explain the method clearly rather than put too much in a short paper. The spacing effect can be done very soon. Hopefully, you will like it.

Hi, Xiaohu

As you pointed out before, the SiN are usually patterned periodically. The spacing effect is of more interest to device strain engineering. So we did new calculation and obtained the results. Here is the link of this post or pdf file of the results.

From the curves we plotted, the spacing effect is quite small except that the SiN stripes are quite close to each other, e.g. S/h<1, where S is spacing, h thickness. So for real application, e.g. S/h>1, the spacing effect maybe not a big concern.

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