When the dielectric constant of an insulator in an interconnect is reduced, mechanical properties are often compromised, giving rise to significant challenges in interconnect integration and reliability. Due to low adhesion of the dielectric an interfacial crack may occur during fabrication and testing. To understand the effect of interconnect structure, an interfacial fracture mechanics model has been analyzed for patterned films undergoing a typical thermal excursion during the integration process. It is found that the underlayer pattern generates a driving force for delamination and changes the mode mixity of the delamination. The implications of our findings to interconnect processes and reliability testing have been discussed.

Low dielectric constant (low-k) is achieved often at the cost of degraded mechanical properties, making it difficult to integrate the dielectric in the back end of line (BEOL) and to package low-k chips. Development of low-k technology becomes costly and time-consuming. Therefore, more frequently than before, people resort to modeling to understand mechanical issues and avoid failures. In this paper we present three multilevel patterned film models to examine channel cracking in low-k BEOL. The effects of copper features, caps and multilevel interconnects are investigated and their implications to BEOL fabrication are discussed.

Low-k BEOL Mechanical Modeling
Liu, Xiao Hu; Lane, Michael W; Shaw, Thomas M; Liniger, Eric G; Rosenberg, Robert R; Edelstein, Daniel C
Advanced Metallization Conference 2004 (AMC 2004); San Diego, CA and Tokyo; USa and Japan; 19-21 Oct. 2004 and 28-29 Sept. 2004. pp. 361-367. 2005