There are several openings for semiconductor process integration at IBM Microelectronics. The reqiured background is quite broad, specifically mechanical engineering background, reliability, failure analysis and modeling with experience in BEOL process and integration. To see more details and to apply online, please click the link below.

https://jobs3.netmedia1.com/cp/job_summary.jsp?job_id=STG-0424220

Packaging mechanical engineers conduct simulation of electronic packages
to optimize package design for compatibility with assembly processes
and for reliable operation in end user systems such as servers, game
consoles and network switches. Simulation is conducted using commercial
finite element software such as ANSYS or ABAQUS to predict package
component stresses and strains. Simulations are verified by measurements
of warpage and stresses / strains in the packages using Digital image
contrast, strain gages, capacitance meters, etc. Package material
properties such as coefficient of thermal expansion, Poisson ratio and
modulus that are required for simulation are measured using specialized
mechanical equipment. Thus, familiarity with numerical simulation

We are looking for an intern to join us this summer at IBM TJ Watson Research Center. You can find the job description at the link below. Please send your resume to apply for it there. More specifically, a background in molecular dynamics is required, and an experience of running open source MD code on supercomputer is preferred. The job will be filled quickly, and you are advised to apply as soon as possible.

When the dielectric constant of an insulator in an interconnect is reduced, mechanical properties are often compromised, giving rise to significant challenges in interconnect integration and reliability. Due to low adhesion of the dielectric an interfacial crack may occur during fabrication and testing. To understand the effect of interconnect structure, an interfacial fracture mechanics model has been analyzed for patterned films undergoing a typical thermal excursion during the integration process. It is found that the underlayer pattern generates a driving force for delamination and changes the mode mixity of the delamination. The implications of our findings to interconnect processes and reliability testing have been discussed.

Low dielectric constant (low-k) is achieved often at the cost of degraded mechanical properties, making it difficult to integrate the dielectric in the back end of line (BEOL) and to package low-k chips. Development of low-k technology becomes costly and time-consuming. Therefore, more frequently than before, people resort to modeling to understand mechanical issues and avoid failures. In this paper we present three multilevel patterned film models to examine channel cracking in low-k BEOL. The effects of copper features, caps and multilevel interconnects are investigated and their implications to BEOL fabrication are discussed.

Low-k BEOL Mechanical Modeling
Liu, Xiao Hu; Lane, Michael W; Shaw, Thomas M; Liniger, Eric G; Rosenberg, Robert R; Edelstein, Daniel C
Advanced Metallization Conference 2004 (AMC 2004); San Diego, CA and Tokyo; USa and Japan; 19-21 Oct. 2004 and 28-29 Sept. 2004. pp. 361-367. 2005