Hi,

 I am researching delaminated composite plates.

 How can i model the delamination area in two plies, is abaqus a correct choice for modelling?

 Delamination area is rectangular or circular.

 Regards.

Hi

I want to know how we can define a Gap Element In ABAQUS

I am doing a research about simulating a delaminated plate by FE Gap Elements

 Please Help

Thanks an advance

H. Mei, Y. Pang, and R. Huang, International Journal of Fracture 148, 331-342 (2007).

Following a previous effort published in MRS Proceedings, we wrote a journal article of the same title, with more numerical results. While the main conclusions stay the same, a few subtle points are noted in this paper.

First, instead of using the approximate formula by Ye, Suo and Evans (1992), we calculate the energy release rate of interfacial delamination emanating from the channel crack exclusively by the finite element method. We found that the approximate formula is not accurate in several cases.

In flip-chip package, the mismatch of thermal expansion coefficients between the silicon die and packaging substrate induces concentrated stress field around the edges and corners of silicon die during assembly, testing and services. The concentrated stresses result in delamination on many interfaces on several levels of structures, in various length scales from tens of nanometers to hundreds of micrometers. A major challenge to model flip-chip packages is the huge variation of length scales, the complexity of microstructures, and diverse materials properties. In this paper, we simplify the structure to be silicon/substrate with wedge configuration, and neglect the small local features of integrated circuits. This macroscopic analysis on package level is generic with whatever small local features, as long as the physical processes of interest occur in the region where the concentrated stress field due to chip-packaging interaction dominates. Because it is the same driving force that motivates all of the flaws. Therefore, the different interface cracks with same size and same orientation but on different interfaces should have similar energy release rates provided that the cracks are much smaller than the macroscopic length. We calculate the energy release rate and the mode angle of crack on the chip-package interface based on the asymptotic linear elastic stress field. In a large range of crack length, the asymptotic solution agrees with finite element calculation very well. We discuss the simplified model and results in context of real applications. In addition, we find that the relation of energy release rate G and crack length a is not power-law since local mode mixity is dependent of crack length a. Therefore, the curve of G~a can be wavy and hardly goes to zero even if crack length a goes to atomically small. The local mode mixity plays an important role in crack behavior.

Channeling cracks in low-k dielectrics have been observed to be a key reliability issue for advanced interconnects. The constraint effect of surrounding materials including stacked buffer layers has been studied. This paper analyzes the effect of interfacial delamination on the fracture condition of brittle thin films on elastic substrates. It is found that stable delamination along with the growth of a channel crack is possible only for a specific range of elastic mismatch and interface toughness. An effective energy release rate is defined to account for the influence of interfacial delamination on both the driving force and the fracture resistance, which can be significantly higher than the case assuming no delamination.

As another celebration of March Journal Club of Mechanics of Flexible Electronics, this paper has just been submitted.

Abstract 

In one design of flexible electronics, thin-film islands of a stiff material are fabricated on a polymeric substrate, and functional materials are grown on these islands. When the substrate is stretched, the deformation is mainly accommodated by the substrate, and the islands and functional materials experience relatively small strains. Experiments have shown that, however, for a given amount of stretch, the islands exceeding a certain size may delaminate from the substrate. We calculate the energy release rate using a combination of finite element method and complex variable method. Our results show that the energy release rate diminishes as the island size or substrate stiffness decreases. Consequently, the critical island size is large when the substrate is compliant. We also obtain an analytical expression for the energy release rate of debonding islands from a very compliant substrate.

When the dielectric constant of an insulator in an interconnect is reduced, mechanical properties are often compromised, giving rise to significant challenges in interconnect integration and reliability. Due to low adhesion of the dielectric an interfacial crack may occur during fabrication and testing. To understand the effect of interconnect structure, an interfacial fracture mechanics model has been analyzed for patterned films undergoing a typical thermal excursion during the integration process. It is found that the underlayer pattern generates a driving force for delamination and changes the mode mixity of the delamination. The implications of our findings to interconnect processes and reliability testing have been discussed.