Stress-induced voiding (SIV) is investigated in Cu-based, deep-submicron, dual damascene technology. Two failure modes are revealed by TEM failure analysis. For one mode, voids are formed under the via when the via connects a wide metal lead below it. For the via which is instead under a wide metal line, voids are formed right above the via bottom. The void source results from the supersaturated vacancies which develop when Cu is not properly annealed after electroplating and before being constrained by dielectrics. The driving force comes from the stress built up due to grain growth and the thermal expansion mismatch (CTE) between Cu interconnect and dielectrics. A diffusion model is introduced to investigate the voiding mechanism primarily for the vias connected to wide metal leads.