Stress-induced voiding (SIV) is investigated in Cu-based, deep-submicron, dual damascene technology. Two failure modes are revealed by TEM failure analysis. For one mode, voids are formed under the via when the via connects a wide metal lead below it. For the via which is instead under a wide metal line, voids are formed right above the via bottom. The void source results from the supersaturated vacancies which develop when Cu is not properly annealed after electroplating and before being constrained by dielectrics. The driving force comes from the stress built up due to grain growth and the thermal expansion mismatch (CTE) between Cu interconnect and dielectrics. A diffusion model is introduced to investigate the voiding mechanism primarily for the vias connected to wide metal leads.

Dislocations are common in epitaxial systems. For a thin film epitaxially grown on a substrate with coherent interface, it may have spontaneously-formed dislocations when its thickness is larger than certain value, i.e. critical thickness. The presence of dislocations can have an adverse effect on electrical performance of semiconductor materials, providing easy diffusion paths for dopants to lead to short circuits, or recombination centers to reduce carrier density. And, formation of dislocations is one of the most observed mechanisms of relaxation of mismatch strain. However, in optoelectric applications, strain alters the electronic bandgap and band edge alignment, and should be maintained. So, controlling formation of dislocations is very important in the manufacture of microelectronic and optoelectronic devices.

This term paper will review some basic concepts and try to produce some understanding about the control dislocation formation.

Today low-k dielectric materials are integrated into computer chips to improve the operation speed and reduce the cross-talk noise. Due to weak mechanical properties of low-k dielectric materials, cohesive failure is subjected to occur. Channel cracking is one common mode of cohesive failure. In this term paper, several potential issues relevant to channel cracking of low-k dielectric thin films are reviewed. These issues include the well known substrate constrain effect; the concentration of crack driving force due to patterned structure, and the degrading of fracture toughness as scaling down the dielectric constant of the films. Some design rules of applying the low-k dielectric thin films are also discussed in this report.

For films or coatings deposited on substrate at high temperature, residual compressive stresses are often induced in the surface layers because of the mismatch in the thermal expansion coefficients. Under such compressive residual stresses, the surface thin film is susceptible to buckling-driven delamination. Various shapes of buckled region are observed, including long straight-sided blisters, circular and the ‘telephone cord’ blister.