The exponential growth in integrated device density has yielded high-performance microprocessors containing almost 1 billion transistors per chip for the current 65 nm technology. Continuous scaling of the devices and performance requires innovations in materials, processes, and designs for both back-end-of-line (BEoL) interconnects and packaging structures. Mechanical reliability has been a limiting factor for implementation of new materials and processes.

X. Zhang, S. H. Im, R. Huang, P. S. Ho, Chapter 2 in Integrated Interconnect Technologies for 3D Nanoelectronic Systems (Editors: M. Bakir and J. Meindl), Artech House, Norwood, MA, 2008. 

Abstract: 

H. Mei, Y. Pang, and R. Huang, International Journal of Fracture 148, 331-342 (2007).

Following a previous effort published in MRS Proceedings, we wrote a journal article of the same title, with more numerical results. While the main conclusions stay the same, a few subtle points are noted in this paper.

First, instead of using the approximate formula by Ye, Suo and Evans (1992), we calculate the energy release rate of interfacial delamination emanating from the channel crack exclusively by the finite element method. We found that the approximate formula is not accurate in several cases.