Abstract
Continuous scaling of high-performance Ultra Large Scale Integrated (ULSI) circuits requires the integration of low dielectric constant (low-κ) materials for interconnect structures. However, low k material is mechanically weak and has low fracture toughness. One of the major failure mechanism observed for low k films during the wafer manufacturing process is channel cracking, in which the cracks propagate in the film plane. When multilayer structures like cu/low k interconnects are manufactured, a large thermal stress will be generated in the film because of the stiffness and CTE difference between cu and low k materials, which may lead to channel cracking in the low k films. In this study, the mechanics of channel cracking will be analyzed and analytical solution is deduced following Prof. Suo’s method. Experimental measurement of the film toughness is also covered. A finite element model is used to simulate the channel cracking in low k films. Effect of multilayer structure configuration such as buffer layer, Cu pad gap width and film thickness on channel cracking is investigated.   

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