Revision of A review on Chip-Package Interaction and Its Impact on Reliability of Cu/low k Interconnects from Fri, 2008-01-18 02:58

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Rui Huang's picture

Chip-packaging interaction is
becoming a critical reliability issue for Cu/low k chips during assembly into a
plastic flip-chip package. In a flip-chip package, the thermal deformation of
the package can be directly coupled into the Cu/low k interconnect structure
inducing large driving forces for interfacial crack formation. This chapter
summarizes the experimental and modeling studies to investigate the
chip-package interaction and its impact on low k interconnect reliability.
First, the packaging induced deformation and stress at the chip level is
analyzed using high-resolution moiré interferometry and compared to thermal and
process-induced stresses during chip fabrication. Then, results from 3D finite
element analysis (FEA) based on a multilevel sub-modeling approach to
investigate the chip-package interaction for low k interconnects is presented.
Packaging induced crack driving forces for relevant interfaces in Cu/low k
structures are deduced and compared with corresponding interfaces in Cu/TEOS
structures. Effects due to the solder, underfill and low k material properties
on packaging reliability are examined. Finally, the effects of interconnect
scaling and multilevel stacking on chip-package interaction and their impact on
low k interconnect reliability is discussed.

Outline:

 

1. Introduction

2. Experimental Techniques

2.1 Thermal deformation of plastic
flip-chip package

2.2 Measurement of interfacial fracture
toughness

3. Mechanics of Cohesive and Interfacial Fracture
in Thin Films

3.1 Channel cracking

3.2 Interfacial delamination

4. Modeling of Chip-Packaging Interactions

4.1. Multilevel sub-modeling technique

4.2 Modified virtual crack closure (MVCC)
method

4.3 Package level deformation

4.4 Energy release rate for stand-alone
chips

 

5. Energy Release Rate under Chip-Package Interactions

5.1 Effect of low k dielectrics

5.2 Effect of solder materials and die
attach process

5.3 Effect of low k material properties

6. Effect of Interconnect Scaling and Ultra
Low k Integration

7. Summary

Acknowledgments

References


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CPI_Review2007.pdf1.6 MB