iMechanica - Journal Club Theme of March 15: Impact of Chip-Package Interaction on Reliability of Copper/Low k Interconnects and Beyond - Comments

thermal fatigue of thin films

Rui Huang — Wed, 08 Oct 2008 10:37:00 -0400

Bob Keller's comment reminded me of their works on thermal fatigue of thin metal films and interconnects.

dicing

Ting Tsui — Tue, 08 Apr 2008 13:58:18 -0400

Hi Zhigang,

This is quite important for the industry since a considerable among of efforts and "real estate" at the die edges are allocated for dicing. If one can develop a good understanding in this area, companies can print chips closer to each other and produce more products on each wafer. High speed fracture seems a difficult problem to understand because hard to "visual" the actual failures. Delamination is the most often observed failure mode but silicon cracking is also commonly reported. IBM papers list by Zhen Zhang are excellent examples.

Regards
Ting

Dr. Philip Garrou's blog on 3D integration

Rui Huang — Fri, 04 Apr 2008 19:33:53 -0400

click http://www.semiconductor.net/blogger/3068.html to learn more about the current developments in 3D technology.

Re: fatigue of interconnects and packages

Xiaodong Li — Tue, 01 Apr 2008 19:20:00 -0400

Thanks Rui. I have just read the paper -

M. Huang, Z. Suo, and Q. Ma, "Plastic ratcheting induced cracks in thin film structures". Journal of the Mechnaics and Physics of Solids, 50, 1079-1098 (2002).

This paper helps me a lot in understanding the plastic deformation and crack initation. I will follow up to do more experiments and hope I can report some results in the future here.

some papers

Zhen Zhang — Mon, 31 Mar 2008 13:36:00 -0400

Hi Zhigang,

Here are two papers about CPI and some experimental pictures. The delamination induced by dicing is huge.

Liu XH et al, @ IITC 2007

Lane M et al @ Adhesion Annual Meeting 2008.

resouces to learn about challenges in the semiconductor industry

Zhigang Suo — Sat, 29 Mar 2008 11:38:00 -0400

Here are two resouces:

International Technology Roadmap for Semiconductors. On this site you can download the famous Roadmaps, the industrial consensus of how to reach the moving target. The target, of course, has been to make Moore's law real. The Roadmaps spell out future needs of the industry, which drive today's research and development.
JEDEC. The developer of standards for the solid-state industry. All publications are free online. For example, JEP112 is entitled "Failure Mechanisms and Models for Silicon Devices".

Any more detailed description of dicing chips?

Zhigang Suo — Sat, 29 Mar 2008 10:42:00 -0400

Dear Ting: I'm intrigued by your description of dicing chips. Do you have more detailed description of the problem? How significant the problem is in terms of waste of wafer and reliability? Do you have any references? This problem sounds like a good one for a joint theoretical and experimental study.

CPI

charliezhai — Fri, 28 Mar 2008 19:01:14 -0400

I want to chime in to echo Jeff's points.

The CPI has a number of financial impact on the semiconductor industry. When it first emerged as a major yield and reliability problem in 90nm node, it has forced the industry to scramble to either go with low-Tg underfill, which exposed the solder bumps to greater jeopardy, or go with chip level process change to mitigate the risk, such as adding polyimide stress buffer to the nitride passivation or crack stops. All these efforts will impact either yield or shift the reliability problems to elsewhere.

I personally still don't think the CPI problem is totally going away once we migrate to ULK and lead-free. However we do have much higher confidence as we have a good understanding now.

The financial impact of CPI

Jie-Hua Zhao — Tue, 25 Mar 2008 16:20:18 -0400

Rui,

One more point of the importance of CPI is its financial impact. Semiconductor industry has a total revenue of $270-300 billion per year world wide. The Cu-low-k BEOL is mainly used in high performance devices, such as CPUs, GPUs, DSPs, wireless application chips, and tele-communication basestation chips. If we count the revenue of Intel, AMD, IBM, nvidia and TI, we will know that there are more than $50 billion worth of products involve the CPI effect every year. This is a good example that how mechanicians, such as Dr. Lei Mercado, can make a difference to the economy.

Jeff

Beyond Cu/low k

Rui Huang — Tue, 25 Mar 2008 13:58:26 -0400

Dear Jeff,

Thank you very much for your comment. I agree with you that it is important for academics and industry to work together on practical issues in technology development, echoing a prior comment by Zhigang. In particular, since the CPI effect on Cu/low k interconnects is now fairly well understood by the industry, what are the practical issues looking beyond Cu/low k technology? Comments from industrial researchers like you would be very helpful to develop collaborations between academics and industry.

Remedies to CPI damage

Jie-Hua Zhao — Mon, 24 Mar 2008 23:38:54 -0400

The so-called chip-package-interaction (CPI) effect was first discovered by my colleague Dr. Lei Mercado at Motorola around late 1999 and early 2000. At that time, Cu-oxide Back-End-of-the-Line (BEOL) was qualified. Motorola Semiconductor Products Sector (now Freescale Semiconductor) was working on Cu-low-k BEOL. It was found that even after a long time struggling on optimizing low-k integration process, when packaging the good dies (passed probe test), the packaging yield was very low. The fab people blamed the packaging people and packaging people said there was no change of packaging process flow. Lei's FEM model revealed that the package-generated crack dirving force (energy release rate) can be as high as one to two orders of that in stand-alone wafers under thermal load. Since then the industry started to recognize the CPI effect. That was the old story. Recent development was summarized well by the reviews of Profs. Ho and Huang.

Today, I think most of the companies working on low-k BEOL know how to mitigate the CPI induced damage. There are a lot of patent applications around the mitigation schemes. The remedies fall into two major catogeries. One is the optimization of the chip. The other is the optimization of the package. From the chip side, one can do a lot of things on process optimization to build tougher interfaces, to produce stronger low-k materials. Another trick is putting dummy structures in BEOL to arrest cracks in the IC design layout, which is of course a good patent topic. From the packaging side, one can choose proper solder alloy (softer) for flip-chip bumps and proper underfill materials (CTE matches solder). Some of the good forums of discussing the packaging optimization are ECTC (www.ectc.net) and ITherm (www.itherm.org).

I realized recently that some chip design software developers are trying to build the IC layout optimization into their software tools. However, the primitive versions tend to optimize the layout to minimize the stress on stand-alone wafers. The CPI effect is totally neglected. This may lead to bad layout design, which is dangerous.

I am glad iMechanica chooses this topic as the Journal Club Theme for this month. I hope more and more mechanicians will pay attention to real industry problems, such as the CPI issue.

fatigue of interconnects and packages

Rui Huang — Mon, 24 Mar 2008 11:36:00 -0400

Xiaodong,

Thanks for the paper. I am not familar with any studies on faitigue of interconnects. Thermal cycling is a standard test for both interconnect and packaging structures, and some failure mechanisms under thermal cycling have been studied, which may include fatigue as well as other mechanisms. For example, Zhigang and his coworkers discovered a ratcheting mechanism that causes fracture of brittle passivation films on metal interconnects after thermal cycles. A few other failure modes were also mentioned in the following paper:

M. Huang, Z. Suo, and Q. Ma, "Plastic ratcheting induced cracks in thin film structures". Journal of the Mechnaics and Physics of Solids, 50, 1079-1098 (2002).

Micro/Nano mechanical and thermal fatigue

Xiaodong Li — Sun, 23 Mar 2008 15:53:00 -0400

Thank you Rui. This is a very nice topic. I have learned a lot from the discussion here. As the interconnects are getting smaller, nanomechanics plays more important roles. I can see issues like mechanical and thermal fatigue of interconnects. I have done some experiments on nanofatigue of Si nanostructures for MEMS/NEMS (see below).

Xiaodong Li and Bharat Bhushan, "Fatigue Studies of Nanoscale Structures for MEMS/NEMS Applications Using Nanoindentation Techniques," Surface and Coatings Technology, 163-164 (2003) 503-508.

I would like to see if there are any papers about fatigues of interconnects. I would like to learn more about this topic. Thank you for your help.

crack stopper during dicing

Ting Tsui — Wed, 19 Mar 2008 16:45:52 -0400

Hi Rui,

This is a very nice topic and the literatures are well represented of the field. The crack stopper at the die edges not only to deflect or stop crack propagations but also prevent moisture to diffuse into the center of the die. This is particularly important because of the high water diffusivity in ULK porous materials.

For the past ten years, most of the IC mechanics studies are focused on the sub-critical or "slow" speed crack propagation behaviors. I was wondering if the fracture results by these experiments is applicable for failures observed during the high speed dicing for chips - the first step of packaging. If we can minimized the damage zone by the high speed saw, we can reduce the scribe line width (i.e., more chips per wafer) and defect initiations. I understand parameters, such as saw blade speed and blade geometries, are very important but seems like very little solid mechanic theoreties developed in this area - high speed impact fracture in nanometer scale. May be you have more experiences on the differences between slow vs high speed small scale fractures.

Ting

package-induced driving force at interconnect level (local)

Rui Huang — Tue, 18 Mar 2008 17:27:20 -0400

Hi Zhen,

Your analogy to gravity is a little off base. By no means I imply the local interconnect structure would significantly affect the global driving force at the package level. However, when we talk about fracture at the interconnect level, the local material structure matters. The k-annulus is large enough to enclose the whole interconnect region, but it cannot give the detailed information about fracture of specific interfaces (e.g., M1 vs M5), since the analysis is based on a homogenized model. It was found that interfaces at upper interconnect levels are more prone to fracture, espectially when low k materials are used selectively at the upper levels. However, observations seem to show that a crack nucleated at the upper level may propagate into lower levels, which may cause further damage to the front-end devices. Both the fracture driving force and mode mix would be needed to simulate the crack propagation in the interconnect structures. That is quite a challenge to me at least.

Journal Club Theme of March 15: Impact of Chip-Package Interaction on Reliability of Copper/Low k Interconnects and Beyond

Rui Huang — Fri, 14 Mar 2008 23:20:02 -0400

The exponential growth in integrated device density has yielded high-performance microprocessors containing almost 1 billion transistors per chip for the current 65 nm technology. Continuous scaling of the devices and performance requires innovations in materials, processes, and designs for both back-end-of-line (BEoL) interconnects and packaging structures. Mechanical reliability has been a limiting factor for implementation of new materials and processes.

Since 1997, copper (Cu) has been selected as the interconnect material to replace aluminum (Al) for two major reasons: (1) Cu has a lower electrical resistivity than Al, thus reducing the R-part of RC delay; (2) Cu has a higher melting point than Al, thus reducing diffusional creep and related reliability concerns such as stress migration and electromigration. However, implementation of Cu interconnects required new processes, such as Cu electroplating, damascene processes, and chemical-mechanical planarization (CMP), which led to a series of new reliability issues. At the 90 nm technology node (around 2002), dielectric materials with k (relative dielectric constant) lower than silicon dioxide (SiO2, k ~ 4) were implemented into the Cu interconnects, to reduce the C-part of RC delay. Implementation of low k dielectrics has posed even more challenges for at least three reasons: (1) There are many possible new materials, but no clear winner; (2) Most of low k materials are mechanically weak (low modulus, low fracture toughness); and (3) Integration of low k materials with other materials is difficult due to large mismatch in thermal expansion coefficients and poor adhesion. As the technology advances, the interconnect structure continues to evolve with decreasing dimensions and increasing complexity in materials and structures. At this time, the effort of the microelectronics industry is focused on implementing ultra-low k porous dielectric materials (k < 2.5) into Cu interconnects to further reduce the RC delay. Meanwhile, the packaging technology for advanced integrated circuits has also been evolving, with the implementation of plastic substrates along with multilayered high-density wiring and solder balls in flip-chip packages. The environmental safety mandates the change from Pb-based solders to Pb-free solders, which are more prone to thermal cyclic fatigue and electromigration reliability problems.

Traditionally, reliability problems for BEoL interconnects and packaging are addressed separately, due to different materials, processes, and dimensions. Recently it is found that Cu/low k interconnects often fail after incorporating the silicon dies into plastic flip-chip packages, raising the concern of chip-package interaction (CPI) as a critical reliability challenge. Different from a stand-alone silicon die, the thermal deformation of the packaging structure can be directly coupled into the Cu/low k interconnects, inducing large local stresses to drive fracture and delamination (see figure below). Depending on the solder materials, the reflow temperature is about 160°C for eutectic Pb alloys and about 250°C for Sn-based Pb-free solders. During accelerated or cyclic thermal tests, the temperature varies from 25°C to 125°C or 150°C. Although the assembly or test temperatures of the package are considerably lower than the chip processing temperatures, chip-package interaction can induce very different stresses in the interconnect structures, due to the mismatch of the coefficients of thermal expansion (CTEs) between the chip (3 ppm/°C for Si) and the packaging substrate (17 ppm/°C for a plastic substrate). The thermally induced shear stress on the solder balls reaches a maximum at the outermost solder row and increases with the size of the chip. Use of the underfill effectively reduces the shear stress, but causes the package to warp, resulting in large peeling stresses at the die-underfill and die-solder interfaces.

The challenge to address CPI-induced reliability issues lies in all areas, from modeling, designing, to manufacturing and testing. Since CPI-induced failure occurs only after package assembling processes of Si dies containing Cu/low k interconnects, the cycle of trial-and-error (make-and-break) can be long and expensive. Finite element based modeling along with fracture mechanics based reliability analysis has been developed for understanding the impact of CPI on reliability of Cu/low k interconnects. However, grant challenges lie ahead for quantitatively faithful modeling as a guide for optimal design of the interconnect and packaging structures. These include: (1) large difference in dimensions from the packaging level (10^(-2) -10^(-3) m) to the interconnect level (10^(-8) m); (2) complex three-dimensional integrated architecture; (3) diverse materials, often with not well characterized thermomechanical properties; (4) uncertainties in crack nucleation and propagation conditions. Here is a recent review on the current approaches of modeling and experiments as well as the current understanding of the CPI effect . A more focused reference is attached below:

G. Wang, P. S. Ho and S. Groothuis, “Chip-packaging interaction: a critical concern for Cu/low k packaging ”, Microelectronics Reliability 45, 1079-1093 (2005).

One practical approach to preventing CPI induced cracking is to incorporate patterned metal structures around the chip perimeter as a crack stop. Both modeling and experimental measurement of the effective toughness of crack stop structures are critical for the design and reliability. Researchers at IBM TJ Watson Research Center presented their work at the 2007 International Interconnect Technology Conference (IITC), which is summarized in the following paper:

T. M. Shaw, E. Liniger, G. Bonilla, J. P. Doyle, B. Herbst, X. H. Liu, M. W. Lane, “Experimental determination of the toughness of crack stop structures ”, Proc. IEEE International Interconnect Technology Conference, pp. 114-116 (2007).

Beyond the Cu/low k technology, two technology innovations are on the horizon and currently under investigation. First, to further reduce the RC delay, implementation of air-gaps in the trench dielectric levels has been demonstrated as a potential solution (e.g., an IBM air-gap structure ). However, it remains a challenging problem to design and fabricate air-gap interconnect structures with satisfactory reliability at an acceptable cost. Collapse of bridging low k cap (or hard mask) over wide air gaps has been observed during thermal decomposition of gap forming materials. The keyhole shaped air gaps by etchback and non-conformal refill schemes may behave as sites of stress concentration, thus prone to cracking. As packaging assembly exerts additional stresses to the fragile air-gap structures, chip-package interaction may cause more serious reliability issues. An introduction to the integration and reliability issues of air-gap interconnect structures is attached here:

R. Hoofman, R. Daamen, J. Michelon, V. Nguyenhoang, “Alternatives to low-k nanoporous materials: dielectric air-gap integration”, Solid State Technology 49, 55-58 (August 2006).

Further down the technology roadmap, three-dimensional (3D) integration of interconnects and packaging is being considered to dramatically enhance chip performance, functionality, and device density (see figure for an illustration). Researchers at IBM and IMEC are leading the way investigating key technology challenges of 3D architectures; two of their papers are attached below. Mechanical reliability remains to be a critical issue, and chip-package interaction becomes inherently relevant for 3D integration. New reliability challenges include: mechanical ramification of high-aspect ratio through-silicon vias (TSVs), handling of dramatically thinned silicon dies, alignment and bonding among stacked wafers, among others. The role of mechanics in the development of 3D technology is yet to be established.

W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, “Three-dimensional integrated circuits ”, IBM Journal of Research and Development 50, 491-506 (2006).
P. De Moor, W. Ruythooren, P. Soussan, B. Swinnen, K. Baert, C. Van Hoof, and E. Beyne, “Recent advances in 3D integration at IMEC”, Mater. Res. Soc. Symp. Proc. 970, No. 0970-Y01-02 (2006).